
Senior Physical Design Engineer
* 12 year physical design/flow development experience in CPU/SOC for server and mobile processors using sub-micron technology nodes including 28nm, 16/12 nm, 10nm, 5nm, and 3nm in various companies which are Intel, Broadcom, Spreadtrum, Apple, and NVIDIA * Moreover, I am specialized in RTL to GDSII including synthesis, LEC, floor planning, clock design, STA, PV, ECOs, VCLP and also proficient in TCL/Perl/Python scripting for design automation and flow development.
apple.com
intel.com
netlogicmicro.com
nvidia.com
broadcom.com
sifive.com
unisoc.com
San Jose, California, United States
Senior Physical Design Engineer
NVIDIA
• www.linkedin.com/company/nvidia
Feb 2022 - Present
United States
Senior Physical Design Engineer
Apple
• www.linkedin.com/company/apple
Jan 2020 - Feb 2022
Cupertino, California
Staff physical design methology engineer
SiFive
• www.linkedin.com/company/sifive
May 2019 - Jan 2020
San Mateo, California
Sr. Staff Physical Design Engineer
Spreadtrum
• www.linkedin.com/company/spreadtrum
Aug 2016 - May 2019
Santa Clara, CA
Physical Design Engineer
Intel Corporation
• www.linkedin.com/company/intel-corporation
Aug 2015 - Aug 2016
Santa Clara, CA
Staff II - IC Design Engineer
Broadcom
• www.linkedin.com/company/broadcom
May 2011 - Aug 2015
Santa Clara, CA
Petty Officer 3rd class
The ROC Navy
Apr 2007 - Mar 2008
Taiwan
Intern
Industry Technology Research Institute (ITRI)
Aug 2005 - Dec 2005
Taiwan
Intern
Aerospace Industrial Development Corporation
Jul 2003 - Aug 2003