I'm a Senior Research Scientist in NVIDIA's Accelerators and VLSI Research Group. I have been writing and publishing research for about 20 years. Recent LLM projects include VerilogEval code gen eval benchmark and creation of ChipNemo. I have a background in circuits and near-threshold voltage scaling, and have expanded my focus to high-level synthesis methodologies (MatchLib, for Siemens EDA Catapult HLS) and LLMs for chip design in recent years. I currently am a member of the International Solid-State Circuits Conference (ISSCC) Digital Architecture and Systems (DAS) technical program committee and of the Accellera SystemC Synthesis Working Group. Please see my list of publications on Google Scholar: https://scholar.google.com/citations?user=v4Nb6ooAAAAJ