Sr. Verification Engineer

* 11+ years experience as a Design Verification engineer contributing to many successful SoC tapeouts * 7+ years experience with UVM methodology deployed in pre-silicon verification * Developed many scalable UVM based environments for block level using constrained-random approach * Experience in developing test plans & verification strategies, implementing testbench using System Verilog and "e", including stimulus sequence generators, functional coverage, monitors, checkers, assertions and scoreboard * Developed Perl scripts to automate the analysis of test results * Protocols : AMBA AXI, AHB, APB, I2C, MMC, JPEG * Languages/Methodologies/Tools: System Verilog, UVM with CDV (Coverage Driven Verification), ’e’, Perl, C, C++, Synopsys tools (VCS, Verdi, dve ), Mentor tools (Questa, Qverify (Formal analysis)) * Result-driven and ability to take over projects with short learning-curves