Senior Mask Design Engineer

Hands-on leader with 22 years’ progressive experience with custom layout of memory and mixed-signal matching techniques, and standard cell library layout experience such as common centroid, critical route, clock signal shielding, power/ground structure and guard ring layout methods. Advanced knowledge and experience using, Laker custom layout design tool and Calibre experience layout verification tool with top level Integration/verification works and CPU IP release. And detailed full chip planning, scheduling Tapeout and release data. Experience with ICC Auto Place&Route tool with Floorplan, ECO, layout edits and DRC/LVS works. Excellent team player and highly motivated in all related layout assignments and provide effective application of engineering requirements. Advice for Contacting In Cho: Directly to Linkedin or at icho2817@yahoo.com