
Senior Mixed Signal Design Validation Engineer
Semiconductor Enthusiast with 12 years of industrial experience, recently focused on ASICs for AI applications. Expertise in HBM/DDR memory systems, and high-speed SerDes interfaces with solid analog design background in power management area. I've led post-silicon validation efforts at top high-tech companies, ensuring robust, reliable, and high-performance silicon solutions. Fueled by innovation and efficiency, I transform complex challenges into pioneering silicon solutions that power tomorrow’s technology.
marvell.com
qualcomm.com
microsoft.com
nvidia.com
maximintegrated.com
apple.com
United States
Senior Mixed Signal Design Validation Engineer
NVIDIA
• www.linkedin.com/company/nvidia
• Full-time
Aug 2025 - Present
Senior Validation Engineer
Microsoft
• www.linkedin.com/company/microsoft
• Full-time
Aug 2022 - Jul 2025
San Francisco Bay Area
Silicon Validation Engineer
Apple
• www.linkedin.com/company/apple
• Full-time
Jun 2020 - Aug 2022
San Francisco Bay Area
Senior System Engineer
Marvell Semiconductor
• www.linkedin.com/company/marvell
• Full-time
Jun 2019 - Apr 2020
San Francisco Bay Area
Senior Applications Engineer
Marvell Semiconductor
• www.linkedin.com/company/marvell
• Full-time
Aug 2017 - Jun 2019
San Francisco Bay Area
Analog Design Engineer
Maxim Integrated
• www.linkedin.com/company/maxim-integrated
• Full-time
May 2013 - Aug 2017
Greater San Diego Area